This invention relates generally to methods of manufacturing multilayer circuit board and multichip modules. More particularly, this invention relates to new and improved methods of manufacturing multilayer circuits wherein interconnections between circuit layers may be accomplished in a single fusion bonding lamination step utilizing a noble metal. In a preferred embodiment, this fusion bonding is accomplished without the need for intermediate bonding plys. Further, this process allows a full range of interconnection and design rules without the need for sequential fabrication, which can significantly reduce process cost by improving yield and decreasing cycle time.
Multilayer circuits are well known and comprise a plurality of stacked substrate/circuit trace assemblies with interconnections between selected locations on the spaced circuit traces. Conventional manufacturing techniques for multilayer circuits generally do not yield multiple levels of interconnect This limits the circuit density and the number of substrates. When multiple interconnect levels are required, step intensive sequential process techniques are usually utilized with reduced yields.
U.S. Pat. No. 4,788,766 attempts to overcome these problems. This prior patent discloses a method wherein a multilayer assembly is made up of a number of individual circuit boards and each board has a substrate on which a first conductive layer is formed on one surface while a second conductive layer is formed on the opposite surface. The substrate is a dielectric material which insulates the conductive layers. Via holes are formed through the first conductive layer, the substrate and the second conductive layer at various locations. An outer conductive material, such as copper, is applied over the first and second conductive layers and onto the side walls of the holes. A conductive bonding material is then deposited onto the outer conductive material in the areas around the holes. Once the individual boards have been fabricated, they are stacked in a predetermined order and orientation with a suitable low temperature dielectric bonding ply (meaning that the bonding ply has a lower softening temperature than the circuit substrate material) positioned between each pair of layers. The dielectric bonding ply requires registered apertures therethrough which correspond to areas where the conductive layer of one substrate is to make an electrically conductive connection with the conductive layer of an adjacent substrate. Thus, the dielectric bonding ply integrally bonds adjacent boards together while providing electrical isolation and/or electrical connections between conductive layers of different boards. The assembly of boards is then subjected to a cycle of heat and pressure to effect a bond between the various board layers.
While the method of U.S. Pat. No. 4,788,766 overcomes some of the problems in the prior art, this prior method has certain disadvantages including the requirement for a substrate which has a melting temperature above the melting temperature of the bonding ply. In other words, the prior patent necessitates the use of a low temperature bond ply which limits the thermal rating of the multi-layer circuit. In addition, this prior method necessitates registered apertures in the bonding ply (leading to alignment problems) and is limited to multilayer circuits having plated through holes.
U.S. Pat. No. 5,046,238 attempts to overcome these problems. This prior art patent discloses a method wherein a plurality of circuit layers comprised of a dielectric substrate having a circuit formed thereon are stacked, one on top of the other. The dielectric substrate is composed of a polymeric material capable of undergoing fusion bonding such as a fluoropolymeric based substrate. Fusible conductive bonding material (e.g., solder) is applied on selected exposed circuit traces (prior to the stacking step) whereupon the entire stacking is subjected to lamination under heat and pressure to simultaneously fuse all of the substrate and conductive layers together to form an integral multilayer circuit having solid conductive interconnects.
In the first embodiment of U.S. Pat. No. 5,046,238, the discrete circuit layers are each prepared by (1) forming traces and pads on a removable mandrel; (2) laminating a layer of dielectric to the circuit and mandrel; (3) forming an access opening at selected locations through the dielectric layer (using laser, plasma, ion etch or mechanical drilling techniques) to expose selected circuit locations; (4) forming conductive posts in the access openings to a level below the top of the access openings; and (5) providing a fusible conductive material in the access opening. Thereafter, a stack-up is made of a plurality of these discrete circuit layers so that the exposed fusible conductive material contacts selected locations on an adjacent circuit. This stack-up is then subjected to heat and pressure to simultaneously fuse both the several layers of dielectric substrate and fusible conductive material to provide a cohesive fused multilayer circuit board.
In the second embodiment of U.S. Pat. No. 5,046,238, at least one discrete circuit board is made using any suitable technique to define a fusible dielectric substrate having a circuit pattern thereon. Next, a layer of fusible dielectric material having openings through selected locations is placed on the circuit board so that selected locations on the circuit pattern are exposed. Thereafter, a plug of fusible conductive material (e.g., solder) is placed in the openings (using manual, mechanical or like techniques). Next, a second circuit board is stacked on the first board so that the plugs of fusible conductive material align with and contact selected locations on the circuit pattern of the second circuit board. This stack-up is then subjected to heat and pressure to simultaneously fuse both the layers of fusible dielectric and the fusible conductive material to provide a cohesive fused multilayer circuit board.
While the method of U.S. Pat. No. 5,046,238 overcomes some of the problems in the prior art, this prior art method has certain disadvantages including problems commonly encountered with spreading of the solder mass during lamination, and evolution of the flux medium necessary to deoxidize the solder. Further, spreading of the solder mass is dependent on the low viscosity of the solder, the amount of solder and the proximity of other circuit features. Also, it is difficult to evolve all of the flux compound from the internal layers of the printed circuit board thereby presenting a potential long-term reliability problem from residual organics. With continued microminiaturization of circuit features, it was desired to produce circuit boards with feature sizes smaller than that possible using solder.